1 UT54ACS109E dual j-k flip-flops septenber 2010 www.aeroflex.com/logic features ? 0.6 m crh cmos process - latchup immune ? high speed ? low power consumption ? wide operating power supply of 3.0v to 5.5v ? available qml q or v processes ? 16-lead flatpack description the UT54ACS109E is a dual j-k positive triggered flip-flop. a low level at the preset or clear inputs sets or resets the outputs regardless of the other input leve ls. when preset and clear are inactive (high), data at the j and k input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. follow ing the hold time interval, data at the j and k input can be changed without affecting the levels at the outputs. the flip-flops can perform as toggle flip-flops by grounding k and tying j high. they also can perform as d flip-flops if j and k are tied together. the devices are characterized ov er full hirel temperature range of -55 c to +125 c. function table note: 1. the output levels in th is configuration are not gua ranteed to meet the mini- mum levels for v oh if the lows at preset and clear are near v il maximum. in addition, this configur ation is nonstable; that is, it will not persist when either preset or clear return s to its inactive (high) level. pinouts 16-lead flatpack top view logic symbol inputs output pre clr clk j k q q l h x x x h l h l x x x l h l l x x x h 1 h 1 h h l l l h h h h l toggle h h l h no change h h h h h l h h l x x no change 1 2 3 4 5 7 6 16 15 14 13 12 10 11 clr1 j1 k1 clk1 pre1 q1 v ss q1 89 v dd clr2 j2 k2 clk2 pre2 q2 q2 q1 (6) (7) q1 q2 (10) (9) q2 (5) pre1 (4) clk1 (1) clr1 (11) pre2 (14) j2 (12) clk2 (13) k2 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. s c1 r (2) j1 j1 (3) k1 k1 (15) clr2
2 logic diagram operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 pre q clr q k clk j
3 absolute maximum ratings note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational s ections is not recommended. ex posure to absolute maximum ra ting conditions for extended periods may affect device reliability. recommended operating conditions symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd + .3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 3.0 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
4 dc electrical characteristics for the UT54ACS109E 7 ( v dd = 3.0v to 5.5v; v ss = 0v 6 ; -55 c < t c < +125 c) notes: 1. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buffer) times fre quency should no t exceed 3,765pf/ mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifica tion and when design changes may affect th e value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50 mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si) per mil-std-883 method 1019 condition a and section 3.11.2. 8. power dissipation specifi ed per switching output. 9. this value is guaranteed based on characterization data, but not tested. symbol description condition vdd min max unit v il low-level input voltage 1 3.0v 0.9 v 5.5v 1.65 v ih high-level input voltage 1 3.0v 2.1 v 5.5v 3.85 i in input leakage current v in = v dd or v ss 5.5v -1 1 a v ol low-level output voltage 3 i ol = 100 a 3.0v 0.25 v 4.5v 0.25 v oh high-level output voltage 3 i oh = -100 a 3.0v 2.75 v 4.5v 4.25 i os short-circuit output current 2 ,4 v o = v dd and v ss 3.0v -100 100 ma 5.5v -200 200 i ol low level output current 9 v in = v dd or v ss v ol = 0.4v 3.0v 6 ma 5.5v 8 i oh high level output current 9 v in = v dd or v ss v oh = v dd -0.4v 3.0v -6 ma 5.5v -8 p total power dissipation 2, 8 c l = 50pf 5.5v 3.0v 2.9 0.8 mw/ mhz i ddq quiescent supply current v in = v dd or v ss 5.5v 10 a c in input capacitance 5 ? = 1mhz 0v 15 pf c out output capacitance 5 ? = 1mhz 0v 15 pf
5 ac electrical characteris tics for the UT54ACS109E 2 (v dd = 3.0v to 5.5v; v ss = 0v 1 , -55 c < t c < +125 c) symbol parameter v dd minimum maximum unit t plh1 clk to q, q c l = 30pf 3.0v & 3.6v 4 23 ns 4.5v & 5.5v 4 19 c l = 50pf 3.0v & 3.6v 4 27 ns 4.5v & 5.5v 4 23 t phl1 clk to q, q c l = 30pf 3.0v & 3.6v 5 27 ns 4.5v & 5.5v 5 23 c l = 50pf 3.0v & 3.6v 5 31 ns 4.5v & 5.5v 5 27 t plh2 pre to q c l = 30pf 3.0v & 3.6v 1 16 ns 4.5v & 5.5v 1 12 c l = 50pf 3.0v & 3.6v 1 20 ns 4.5v & 5.5v 1 16 t phl2 pre to q c l = 30pf 3.0v & 3.6v 1 19 ns 4.5v & 5.5v 1 15 c l = 50pf 3.0v & 3.6v 1 23 ns 4.5v & 5.5v 1 19 t plh3 clr to q c l = 30pf 3.0v & 3.6v 2 16 ns 4.5v & 5.5v 2 12 c l = 50pf 3.0v & 3.6v 2 20 ns 4.5v & 5.5v 2 16 t phl3 clr to q c l = 30pf 3.0v & 3.6v 2 19 ns 4.5v & 5.5v 2 15 c l = 50pf 3.0v & 3.6v 2 23 ns 4.5v & 5.5v 2 19 f max4 maximum clock frequency c l = 50pf 3.0v, 4.5v, and 5.5v 62 mhz t su1 pre or clr inactive setup time before clk c l = 50pf 3.0v, 4.5v, and 5.5v 5 ns
6 notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si) per mil-std-883 method 1019 condition a and section 3.11.2. 3. based on characterization, hold time (t h ) of 0ns can be assumed if data setup time (t su2 ) is > 10ns. this is guaran teed, but not tested. 4. historically maximum frequency "f max " was based off minimum pulse width (t w ), f max = 1/2t w. in practice, the achievable f max is dictated by the clk to q propagation delays listed in the ac electrical table. for a more complete description on calculating the applicable f max reference, the application note titled ?frequency vs load capacitan ce for the msi product family" is located at www.aeroflex.com/ t su2 data setup time before clk c l = 50pf 3.0v, 4.5v, and 5.5v 5 ns t h 3 data hold time after clk c l = 50pf 3.0v, 4.5v, and 5.5v 3 ns t w minimum pulse width pre or clr low clk high clk low c l = 50pf 3.0v, 4.5v, and 5.5v 8 ns
packaging
8 ordering information UT54ACS109E i/o type: acs = cmos compatible i/o level part number: 109e = dual j-k flip-flops package type: u = 16-lead ceramic bottom-brazed dual-in-line flatpack screening: (note 3) c = hirel temperature range (-55 o c to +125 o c) lead finish: (notes 1 & 2) a = solder c = gold x = optional ut54 *** **** - * ** notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, then the part markin g will match the lead finish and will be either "a" (solder) or " c" (gold). 3. hirel temperature range flow per aeroflex manufacturing flows document. devices have 48 hours of burn-in and are test at - 55 o c, room temperature, and 125 o c. radiation characterisitics are neither tested nor guaranteed and may not be specified.
9 UT54ACS109E: smd drawing number: 96540 = UT54ACS109E device type: 02 = 1 rad(si)/sec package type: x = 16-lead ceramic botto m-brazed dual-in-line flatpack lead finish: (notes 1 & 2) a = solder c = gold x = optional 5962 ***** ** * * * * total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) 03 = 50 to 300 rads(si)/sec class designator: q = qml class q v = qml class v notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2. device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si), and 5e5 rads(si), and is tested in accordance w ith mil-std-883 test method 1019 condition a.
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